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本文介绍一些verilog实现的数字电路的实例。如有错误，欢迎指出，感谢。
1
vga驱动
实验原理：VGA的显示效果取决于输入的RGB的值，R,G,B的值是通过不同的引脚接入的，逐行扫描是扫描从屏幕左上角一点开始，从左像右逐点扫描，每扫描完一行,电子束回到屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行同步；当扫描完所有的行，形成一帧，用场同步信号进行场同步，并使扫描回到屏幕左上方，同时进行场消隐,开始下一帧。
Experimental principle: VGA display effect depends on the input of the RGB values, R, G, B value is through different pin access, progressive scan is to scan from left upper corner of the screen, point by point scanning, from left as right after each scan line, electron beam back to the left of the screen to the next line of the starting position, during this period, the CRT to blanking of electron beam, at the end of each row, Synchronization with line synchronization signal; When all lines have been scanned, a frame is formed, the field sync signal is used for field sync, and the scan is returned to the upper left of the screen, and the field blanking is performed to start the next frame.
核心代码：
The core code:
波形：
wave:
2
数据接收端
实验原理：通过三个寄存器来判断上升沿和下降沿，当请求信号的上升沿出现时就开始启动接收数据当检测到下降沿时就接收数据完成，然后发送一个高脉冲给数据的发送端表示数据接收完毕。
Experimental principle: three registers are used to judge the rising edge and falling edge. When the rising edge of the request signal appears, it starts to receive data. When the falling edge is detected, the data is received, and then a high pulse is sent to the sender of data to indicate that the data is received.
RTL电路图：
RTL circuit diagram:
核心代码：
The core code:
波形：
wave:
3
UART发送12位数据
实验原理：使用状态机对状态进行切换，使用移位寄存器接收满了8位数据后就重新发送标志位，并重新开始接收。
Use the state machine to switch the state, use the shift register to receive full 8 bits of data on the re-send flag bits, and start receiving again.
核心代码：
The core code:
波形：
wave:
参考资料：
《FPGA/CPLD边学边练》吴厚航著
百度
翻译：谷歌翻译
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